Determines the target generation of Alpha chip for which code
  will be generated for this program.  The /ARCHITECTURE qualifier
  uses the same options (keywords) as the /OPTIMIZE=TUNE (Alpha
  only) qualifier.

  Whereas the /OPTIMIZE=TUNE qualifier is primarily used by certain
  higher-level optimizations for instruction scheduling purposes, the
  /ARCHITECTURE qualifier determines the type of code instructions
  generated for the program unit being compiled.

  OpenVMS Version 7.1 and subsequent releases will provide an
  operating system kernel that includes an instruction emulator.
  This emulator allows new instructions, not implemented on the host
  processor chip, to execute and produce correct results.
  Applications using emulated instructions will run correctly, but
  may incur significant software emulation overhead at runtime.

  All Alpha processors implement a core set of instructions.  Certain
  Alpha processor versions include additional instruction extensions.

  The following /ARCHITECTURE options are supported:

  GENERIC
    Generates code that is appropriate for all Alpha processor
    generations.  This is the default.

    Programs compiled with the GENERIC option run all implementations
    of the Alpha architecture without any instruction emulation
    overhead.

  HOST
    Generates code for the processor generation in use on the system
    being used for compilation.

    Programs compiled with this option run on other implementations of
    the Alpha architecture might encounter instruction emulation
    overhead.

  EV4
    Generates code for the 21064, 21064A, 21066, and 21068
    implementations of the Alpha architecture.

    Programs compiled with the EV4 option run without instruction
    emulation overhead on all Alpha processors.

  EV5
    Generates code for some 21164 chip implementations of the Alpha
    architecture that use only the base set of Alpha instructions (no
    extensions).

    Programs compiled with the EV5 option run without instruction
    emulation overhead on all Alpha processors.

  EV56
    Generates code for some 21164 chip implementations that use the
    byte and word manipulation instruction extensions of the Alpha
    architecture.

    Programs compiled with the EV56 option may incur emulation
    overhead on EV4 and EV5 processors, but will still run correctly
    on OpenVMS Version 7.1 (or later) systems.

  EV6
    Generates code for the 21264 chip implementation that uses the
    following extensions to the base Alpha instruction set:  BWX
    (Byte/Word manipulation) and MAX (Multimedia) instructions,
    square root and floating-point convert instructions, and count
    instructions.

    Programs compiled with the EV6 option may incur emulation
    overhead on EV4, EV5, EV56, and PCA56 processors, but will still
    run correctly on OpenVMS Version 7.1 (or later) systems.

  EV67
    Generates code for chip implementations that use advanced
    instruction extensions of the Alpha architecture. This option
    permits the compiler to generate any EV67 instruction, including
    the following extensions to the base Alpha instruction set: BWX
    (Byte/Word manipulation), MVI (Multimedia) instructions, square
    root and floating-point convert extensions (FIX), and count
    extensions (CIX).

    Programs compiled with the EV67 option may incur emulation
    overhead on EV4, EV5, EV56, EV6 and PCA56 processors, but will
    still run correctly on OpenVMS Version 7.1 (or later) systems.

  PCA56
    Generates code for the 21164PC chip implementation that uses the
    byte and word manipulation instruction extensions and multimedia
    instruction extensions of the Alpha architecture.

    Programs compiled with the PCA56 option may incur emulation
    overhead on EV4, EV5, and EV56 processors, but still run
    correctly on OpenVMS Version 7.1 (or later) systems.