Syntax options:
ARCHITECTURE=GENERIC
ARCHITECTURE=HOST
ARCHITECTURE=EV4
ARCHITECTURE=EV5
ARCHITECTURE=EV56
ARCHITECTURE=PCA56
ARCHITECTURE=EV6
ARCHITECTURE=EV67
ARCHITECTURE=EV68
ARCHITECTURE=EV7
For improved performance of generated code, the ARCHITECTURE
command line qualifier can be used on OpenVMS Alpha systems. The
ARCHITECTURE qualifier is ignored on Itanium systems.
The ARCHITECTURE qualifier specifies the lowest version of the
Alpha architecture where this code will run. This allows the
compiler to generate more efficient code, with the tradeoff that
code may not run on older systems.
All Alpha processors implement a core set of instructions and, in
some cases, the following extensions:
o Byte/word extension (BWX) - The instructions that comprise the
BWX extension are LDBU, LDWU, SEXTB, SEXTW, STB, and STW.
o Square-root and floating-point convert extension (FIX) - The
instructions that comprise the FIX extension are FTOIS, FTOIT,
ITOFF, ITOFS, ITOFT, SQRTF, SQRTG, SQRTS, and SQRTT.
o Count extension (CIX) - The instructions that comprise the CIX
extension are CTLZ, CTPOP, and CTTZ.
o Multimedia extension (MVI) - The instructions that comprise
the MVI extension are MAXSB8, MAXSW4, MAXUB8, MAXUW4, MINSB8,
MINSW4, MINUB8, MINUW4, PERR, PKLB, PKWB, UNPKBL, and UNPKBW.
The Alpha Architecture Reference Manual describes the extensions
in detail.
The keyword specified with the ARCHITECTURE qualifier determines
which instructions the compiler can generate and which coding
rules it must follow.
o GENERIC - Generate instructions that are appropriate for all
Alpha processors. This option is the default and is equivalent
to /ARCH=EV4.
o HOST - Generate instructions for the processor that the
compiler is running on (for example, EV56 instructions on
an EV56 processor, EV7 instructions on an EV7 processor, and
so on).
o EV4 - Generate instructions for the EV4 processor (21064,
20164A, 21066, and 21068 chips). Applications compiled with
this option will not incur any emulation overhead on any Alpha
processor.
o EV5 - Generate instructions for the EV5 processor (some 21164
chips). (Note that the EV5 and EV56 processors both have the
same chip number - 21164.) Applications compiled with this
option will not incur any emulation overhead on any Alpha
processor.
o EV56 - Generate instructions for EV56 processors (some 21164
chips). This option permits the compiler to generate any
EV4 instruction plus any instructions contained in the BWX
extension. Applications compiled with this option may incur
emulation overhead on EV4 and EV5 processors.
o PCA56 - Generate instructions for PCA56 processors (21164PC
chips). This option permits the compiler to generate any EV4
instruction plus any instructions contained in the BWX and MVI
extensions. Applications compiled with this option may incur
emulation overhead on EV4 and EV5 processors.
o EV6 - Generate instructions for EV6 processors (21264
chips). This option permits the compiler to generate any
EV4 instruction, any instruction contained in the BWX and
MVI extensions, plus any instructions added for the EV6
chip. These new instructions include a floating-point square
root instruction (SQRT), integer/floating-point register
transfer instructions, and additional instructions to identify
extensions and processor groups. Applications compiled with
this option may incur emulation overhead on EV4, EV5, EV56,
and PCA56 processors.
o EV67 or EV68 - Generate instructions for EV67 and EV68
processors (21264A chips). This option permits the
compiler to generate any EV6 instruction plus the new bit
count instructions (CTLZ, CTPOP, and CTTZ). However, the
precompilers do not currently generate any of the new bit
count instructions and the EV67 and EV68 have identical
instruction scheduling models so the EV67 and EV68 are
essentially identical to the EV6. Applications compiled with
this option may incur emulation overhead on EV4, EV5, EV56,
and PCA56 processors.
o EV7 - Generate instructions for the EV7 processor (21364
chip). This option permits the compiler to generate any EV67
instruction. There are no additional instructions available
on the EV7 processor but the compiler does have different
instruction scheduling and prefetch rules for tuning code
for the EV7. Applications compiled with this option may incur
emulation overhead on EV4, EV5, EV56, and PCA56 processors.
The OpenVMS Alpha operating system includes an instruction
emulator. This capability allows any Alpha chip to execute and
produce correct results from Alpha instructions even if some of
the instructions are not implemented on the chip. Applications
using emulated instructions will run correctly but may incur
significant emulation overhead at run time.
Of the available extension types, the Byte/word extension (BWX)
will often be beneficial for increased performance of Rdb-based
applications. In addition, for those Alpha implementations
that support quad-issue of instructions (the EV6 and later
processors), the compiler does have different instruction
scheduling and prefetch rules for tuning code.
For highest levels of performance of generated code, Oracle
recommends that the ARCHITECTURE qualifier be specified with
the keyword that most closely matches the lowest processor type
of the machine where the program will execute.
LANGUAGE COMPILER SUPPORT FOR ARCHITECTURE
If specified, the ARCHITECTURE qualifier is passed on the
command line to the specified language compiler by the SQL
Precompiler. The language compiler being used must support
the ARCHITECTURE qualifier and the architecture keyword
value when the ARCHITECTURE qualifier is specified.